PCA9605DP,118

PCA9xxx Bus Buffers

NXP Semiconductors PCA9xxx Bus Buffers include the PCA9512B hot swappable I²C-bus and SMBus buffer, and the PCA9525 and PCA9605 monolithic CMOS integrated circuits for bus buffering in applications including I²C-bus, SMBus, DDC, PMBus, and other systems based on similar principles.

The PCA9512B allows I/O card insertion into a live backplane without corruption of the data and clock buses and includes two dedicated supply voltage pins to provide level shifting between 3.3 and 5V systems while maintaining the best noise margin for each voltage level. Either pin may be powered with supply voltages ranging from 2.7 to 5.5V with no constraints on which supply voltage is higher. Control circuitry prevents the backplane from being connected to the card until a stop bit or bus idle occurs on the backplane without bus contention on the card. When the connection is made, the PCA9512B provides bidirectional buffering, keeping the backplane and card capacitances isolated.

The PCA9525 and PCA9605 buffers extend the bus load limit by buffering both the SCL and SDA lines, allowing the maximum permissible bus capacitance on both sides of the buffer. These buffer ICs include a unidirectional buffer for the clock signal, and a bidirectional buffer for the data signal. Slave devices which employ clock stretching are therefore not supported. The direction pin (DIR) further enhances this function by allowing the unidirectional clock signal to be reversed, thus allowing master devices on both sides of the buffer. The enable (EN) function allows sections of the bus to be isolated. Individual parts of the system can be brought on-line successively. This means a controlled start-up using a diverse range of components, operating speeds, and loads is easily achieved.