Design Gateway SATA3 Host CPUless IP Core
Design Gateway SATA3 Host CPUless IP Core is designed to be an all-in-one system containing the application, transport, and link layers in one IP. This helps the connection with the PHY layer implemented by the transceiver without CPU and DDR usage. The SATA Physical layer is designed using an HDL code to control the transceiver following the SATA protocol. The interface module is connected between the SATA3H-CL IP and the SATA device. This SATA3 IP core PHY is provided in the reference design in the release stuff for the IP customer. The SATA3 host IP core features a dgIF typeS user interface that is very easy to access and comes with a control and data interface.
The control interface includes general input parameters for Write and Read commands, such as start address and transfer length. The data interface for the Write command (Tx FIFO) and Read command (Rx FIFO) is designed by using the general FIFO interface. SATA3 IP core supports four ATA commands. The IDENTIFY DEVICE command checks the SATA device capacity. SECURITY ERASE UNIT erases data on the SATA device. WRITE DMA (EXT) will record data for the SATA device, and READ DMA (EXT) will read data from the SATA device.
Features
- Simple user interface by dgIF types
- Support four commands such as IDENTIFY DEVICE, SECURITY ERASE UNIT, WRITE DMA (EXT), and READ DMA (EXT)
- SATA application layer, transaction layer, and link layer by hardware logic
- No need for external memory and CPU
- Compliant with the Serial ATA specification revision 3.0
- 2 x 4Kbyte FIFO for internal buffer
- Support SATA-III Speed by using 150MHz for the SATA clock and a higher frequency for the user clock
- Free HDL code of SATA3 PHY and the reference design in release stuff
- Reference design by using AB12-HSMCRAID or AB09-FMCRAID adapter board from Design Gateway
Block Diagram
Publié le: 2020-05-31
| Mis à jour le: 2024-06-11