STMicroelectronics SPC57 M Line MCU
STMicroelectronics SPC57 M Line MCU are designed for automotive powertrain controller applications. This includes four-cylinder gasoline and diesel engines, chassis control, transmission control, steering and braking, and low-end hybrid applications. The family is designed to achieve ISO26262 ASIL-A compliance.Features
- 1 main CPU, single issue, 32-bit CPU core complex (e200z2)
- Power Architecture embedded specification compliance
- Instruction set enhancement allowing variable length encoding (VLE), encoding a mix of 16-bit and 32-bit instructions, for code size footprint reduction
- Single-precision floating point operations
- Saturation Instructions Extension adding scalar saturating arithmetic support to the PowerISA Integer Saturation (ISAT)
- 1568KB (1536KB code flash + 32KB data flash) on-chip flash memory
- Supporting multiple blocks allowing EEPROM emulation
- RWW between data EEPROM and code flash memory
- 64KB general-purpose data SRAM
- System Memory Protection Unit (SMPU)
- 16-channel Direct Memory Access controllers (eDMA) with two-channel multiplexers for up to 60 DMA sources
- Interrupt Controller (INTC) supporting up to 1024 interrupt sources (all are not assigned)
- System Timer Module (STM)
- 2 Software Watchdog Timers (SWT)
- 2 Periodic Interrupt Timers (PIT)
- 1 PIT with four standard 32-bit timer channels
- 1 PIT with two 32-bit timer channels which can be combined into one 64-bit channel
- Single phase-locked loop with stable clock domain for peripherals and core (PLL)
- Single crossbar switch architecture for concurrent access to peripherals, flash memory, or SRAM from multiple bus masters
- System Integration Unit Lite (SIUL2)
- Boot Assist Flash (BAF) supports factory programming using a serial bootload through the UART Serial Boot Mode Protocol (physical interface (PHY) can be e.g., UART and CAN)
- PASS module (supporting 256-bit JTAG password protection)
- Device lifecycle monitoring
- Generic Timer Module (GTM101)
- Enhanced analog-to-digital converter system with:
- Three 12-bit SAR analog converters
- One 16-bit Sigma-Delta analog converter
- Decimation unit to support SD ADC data conditioning
- 1 Deserial Serial Peripheral Interface (DSPI) module
- 2 LIN and UART communication interfaces (LINFlexD) modules
- 1 microsecond-bus channel (composed of one DSPI and one LINFlexD)
- 4 SENT (Single Edge Nibble Transmission) channels
- 2 Modular Controller Area Network (M-CAN) modules
- 1 Clock Calibration on CAN Unit (CCCU)
- Fast Ethernet Controller (FEC)
- Fast Asynchronous Serial Transmission (LFAST)
- Nexus Development Interface (NDI) per IEEE-ISTO 5001-2003 standard, with partial support for 2010 standard
- Device and board test support per Joint Test Action Group (JTAG) (IEEE 1149.1 and IEEE 1149.7)
- On-chip voltage regulator controller manages the supply voltage down to 1.2V for core logic
- Self-test capability
Videos
Block Diagram
Additional Resource
Publié le: 2018-12-03
| Mis à jour le: 2023-02-27
