Texas Instruments 66AK2G1x KeyStone II System-on-Chip (SoC)

Texas Instruments 66AK2G1x KeyStone II System-on-Chip (SoC) addresses applications that require both DSP and Arm® performance, with the integration of high-speed peripherals and memory interfaces. This SoC also includes hardware acceleration for network and cryptography functions and high-level operating systems (HLOS) support. The 66AK2G1x enables both the DSP and Arm cores to master all memory and peripherals in the system. This architecture facilitates maximum software flexibility where either DSP or Arm-centric system designs can be achieved.

The 66AK2G1x significantly improves device reliability by extensively implementing error correction code (ECC) in processor cores, shared memory, embedded memory in modules, and external memory interfaces. A full analysis of soft error rate (SER) and power-on-hours (POH) shows that the designated 66AK2G1x parts satisfy a wide range of industrial and automotive requirements.

Features

  • Processor cores
    • Arm® Cortex®-A15 microprocessor unit (Arm A15) subsystem at up to 1000MHz
      • Supports full implementation of Armv7-A architecture instruction set
      • Integrated SIMDv2 (NEON™ Technology) and VFPv4 (Vector Floating Point)
      • 32KB of L1 Program memory
      • 32KB of L1 Data memory
      • 512KB of L2 Memory
      • Error Correction Code (ECC) protection for L1 data memory ECC for L2 memory
      • Parity protection for L1 program memory
      • Global Timebase Counter (GTC)
    • C66x Fixed- and floating-point VLIW DSP subsystem at up to 1000MHz
      • Fully object-code compatible with C67x+ and C64x+ cores
      • 32KB of L1 Program memory
      • 32KB of L1 Data memory
      • 1024KB of L2 Configurable as L2 RAM or cache
      • Error Detection for L1 Program memory
      • ECC for L1 Data memory
      • ECC for L2 Data memory
  • Industrial subsystem
    • Up to two Programmable Real-Time Unit and Industrial Communication Subsystems (PRU-ICSS)
  • Memory subsystem
    • Multicore Shared Memory Controller (MSMC) With 1024KB of shared L2 RAM
    • Up to 36-Bit DDR External Memory Interface (EMIF)
    • General-Purpose Memory Controller (GPMC)
  • Network Subsystem (NSS)
    • Ethernet MAC Subsystem (EMAC)
    • Navigator Subsystem (NAVSS)
    • Crypto Engine (SA)
  • Display subsystem
    • Supports one video pipe with in-loop scaling, color space
    • Conversion and background color overlay
    • Input data format: BITMAP, RGB16, RGB24, RGB32, ARGB16, ARGB32, YUV420, YUV422, and RGB565-A8
    • Supported display interfaces
      • MIPI® DPI 2.0 Parallel interface
      • RFBI (MIPI-DBI 2.0) up to QVGA at 30fps
      • BT.656 4:2:2
      • BT.1120 4:2:2 up to 1920 × 1080 at 30fps
    • In-loop scaling capability
    • LCD Display interface supports
      • Active Matrix (TFT)
      • Passive Matrix (STN)
      • Grayscale
      • TDM
      • AC Bias Control
      • Dither
      • CPR
  • Asynchronous Audio Sample Rate Converter (ASRC)
  • High-speed serial interface
    • PCI Express® 2.0 Port with integrated PHY
    • Up to two USB 2.0 high-speed dual-role ports with integrated PHYs
  • Flash media interfaces
    • QSPI™ with XIP and up to four chip selects
    • Two Multimedia Card (MMC) and Secure Digital (SD) ports
  • Audio peripherals
    • Three Multichannel Audio Serial Port (McASP) peripherals
    • Multichannel Buffered Serial Port (McBSP)
  • Automotive peripherals
    • Two Controller Area Network (CAN) ports
    • One Media Local Bus (MLB)
  • Real-time control interfaces
    • Six Enhanced High-Resolution Pulse Width Modulation (eHRPWM) modules
    • Two 32-Bit Enhanced Capture modules (eCAP)
    • Three 32-Bit Enhanced Quadrature Pulse Encoder modules (eQEP)
  • General connectivity
    • Three Inter-Integrated Circuit (I2C) interfaces
    • Four Serial Peripheral Interfaces (SPI)
    • Three UART interfaces
    • General-Purpose I/O (GPIO)
  • Timers and miscellaneous modules
    • Seven 64-Bit Timers
    • Interprocessor communication
    • EDMA with 128 (2×64) Channels and 1024 (2×512) PaRAM entries
  • Keystone II System on Chip (SoC) architecture
    • Security
    • Power management
    • Supports primary boot from UART, I2C, SPI, GPMC, SD or eMMC, USB device firmware upgrade v1.1, PCIe®, and Ethernet interfaces
    • Keystone II debug architecture with integrated Arm CoreSight™ support and trace capability
  • Operating temperature (TJ)
    • –40°C to 125°C (Automotive)
    • –40°C to 105°C (Extended)
    • 0°C to 90°C (Commercial)

Applications

  • Industrial communications and controls
  • Automotive audio amplifiers
  • Home audio
  • Professional audio
  • Power protection
  • Other embedded systems

Functional Block Diagram

Block Diagram - Texas Instruments 66AK2G1x KeyStone II System-on-Chip (SoC)
Publié le: 2018-07-31 | Mis à jour le: 2023-02-01