The SN74LVC1G08-Q1 Positive-AND Gates are fully specified for partial-power-down applications using Ioff. When powered down, the Ioff circuitry disables the outputs, preventing damaging current backflow through the device. The CMOS SN74LVC1G08-Q1 has a high output drive while maintaining low static power dissipation over a broad VCC operating range.
The Texas Instruments SN74LVC1G08-Q1 is available in various packages, including the small DRY package with a body size of 1.45mm × 1.00mm.
Features
- AEC-Q100 qualified for automotive applications
- Device temperature Grade 1 (–40°C to +125°C, TA)
- Supports 5V VCC operation
- Over-voltage tolerant inputs accept voltages to 5.5V
- Provides down translation to VCC
- Low power consumption, 10µA max ICC
- ±24mA output drive at 3.3V
- Ioff supports live insertion, partial-power-down mode, and back drive protection
- Latch-up performance exceeds 100mA
- Per JESD 78, Class II
- ESD protection exceeds JESD 22
- 2000V human-body model (A114-A)
- 200V machine model (A115-A)
- 1000V charged-device model (C101)
Applications
- Fully qualified for automotive applications
- Combine power good signals for multiple power rails
- Prevent a signal from being passed until a condition is true
- Combine active-low error signals
Functional Diagram
Publié le: 2019-10-16
| Mis à jour le: 2025-02-21

